I’m having timeout problems by running a test sequence with switching steps in a batch model.
A short description of my HW architecture:
A simple schematic can be found in the appendix.
We have 3x a Keysight 34980A Switch Main Frame with 4 active Slot units. 2x a Matrix, 1x a GP- card and 1x Multiplexer.
Communication Bus is LXI.
Used SW:
- NI TestStand 2014 SP1 - using the standard NI Batch process model
- NI Switch Executive 2015
- OS: W7 64bit professional
The goal is to test a batch with 3 DUTs.
My first approach was to define only 1 virtual switch executive which includes all 3 HW Switch frames. Advantage would be that I can connect the matrix card from the 3 HW switch frames with each other over a HW bus realized over the Virginia panel. This possibility is actually not required at the moment but is a design decision for the future. Requirement for the actual DUTs is that each DUT has his dedicated HW- Switch Frame with the corresponding card.
For the test sequence; I have a fix SE- Name for the TestStand Step and a test socket depending route name. The approach works fine for 1 Socket and also for all 3 sockets as long as the tracing is enabled and not too fast.
By disabling the tracing I receive timeout error.
Error:“Could not perform the switching operation: Details: An error has occurred while attempting to access device DAU2 VISA error = Zeitüberschreitung, bevor der Vorgang abgeschlossen werden konnte.(Error = -2147483648)”
translation German part of error message: Timeout error bevor process could be terminated
See screenshot in appendix.
It looks like there are deadlocks when multiple switching commands are sent. See my example sequence.
In a second approach I defined a virtual switch executive unit for each HW Swich Frame: So in this case I have a socket depending switch name and a fix route name. This approach work now with 3 SE- objects in contrast to the first approach with only 1 SE-object.
Using this variant I don’t have the timeout error by running the sequence without tracing enable.
I would like to ask/ discuss why I’m seeing the timeouts in the first approach. Does I do something wrong or is this some kind of restriction from my SW- Design or in general from SE.
Appendix: - NI MAX export including the SE definitions - TestStand example sequence file - Error Screenshot - HW architecture diagram
